----------------------------------------------------------------------------------
-- Company: http://www.mikekohn.net/
-- Engineer: Michael A. Kohn
-- 
-- Create Date:    05:26:41 12/17/2008 
-- Design Name: PCI Blink!
-- Module Name:    pciblink - Behavioral 
-- Project Name: PCI Blink!
-- Target Devices: 5I20
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pciblink is
  Port (lclk: in STD_LOGIC;
        leds: out STD_LOGIC_VECTOR(7 downto 0)
		 );
        
end pciblink;

architecture Behavioral of pciblink is

signal clk: STD_LOGIC_VECTOR (24 downto 0);
signal counter: STD_LOGIC_VECTOR (7 downto 0);

begin
  -- variable counter: STD_LOGIC_VECTOR (7 downto 0);
  
  -- Clock divide by 65536
  process(lclk)
  begin
    if lclk = '1' and lclk'Event then
	   clk <= clk + "1";
		
		if clk = "000000000000000000000000" then
		  counter <= counter + 1;
		end if;
	 end if;
  end process;

  leds <= counter;

end Behavioral;